The present invention relates to non-volatile memories and, more particularly, to flash memories, especially flash memories that store several bits per cell.
Flash memory devices have been known for many years. Typically, each cell within a flash memory stores one bit of information. Traditionally, the way to store a bit has been by supporting two states of the cell—one state represents a logical “0” and the other state represents a logical “1”. In a flash memory cell the two states are implemented by having a floating gate above the cell's channel (the area connecting the source and drain elements of the cell's transistor), and having two valid states for the amount of charge stored within this floating gate. Typically, one state is with zero charge in the floating gate and is the initial unwritten state of the cell after being erased (commonly defined to represent the “1” state) and another state is with some amount of negative charge in the floating gate (commonly defined to represent the “0” state). Having negative charge in the gate causes the threshold voltage of the cell's transistor (i.e. the voltage that has to be applied to the transistor's control gate in order to cause the transistor to conduct) to increase. Now it is possible to read the stored bit by checking the threshold voltage of the cell—if the threshold voltage is in the higher state then the bit value is “0” and if the threshold voltage is in the lower state then the bit value is “1”. Actually there is no need to accurately read the cell's threshold voltage—all that is needed is to correctly identify in which of the two states the cell is currently located. For that purpose it suffices to make a comparison against a reference voltage value that is in the middle between the two states, and thus to determine if the cell's threshold voltage is below or above this reference value.
FIG. 1A shows graphically how this works. Specifically, FIG. 1A shows the distribution of the threshold voltages of a large population of cells. Because the cells in a flash device are not exactly identical in their characteristics and behavior (due, for example, to small variations in impurity concentrations or to defects in the silicon structure), applying the same programming operation to all the cells does not cause all of the cells to have exactly the same threshold voltage. (Note that, for historical reasons, writing data to a flash memory is commonly referred to as “programming” the flash memory. The terms “writing” and “programming” are used interchangeably herein.) Instead, the threshold voltage is distributed similar to the way shown in FIG. 1A. Cells storing a value of “1” typically have a negative threshold voltage, such that most of the cells have a threshold voltage close to the value shown by the left peak of FIG. 1A, with some smaller numbers of cells having lower or higher threshold voltages. Similarly, cells storing a value of “0” typically have a positive threshold voltage, such that most of the cells have a threshold voltage close to the value shown by the right peak of FIG. 1A, with some smaller numbers of cells having lower or higher threshold voltages.
In recent years a new kind of flash device has appeared on the market, using a technique conventionally called “Multi Level Cells” or MLC for short. (This nomenclature is misleading, because the previous type of flash cells also has more than one level: they have two levels, as described above. Therefore, the two kinds of flash cells are referred to herein as “Single Bit Cells” (SBC) and “Multi-Bit Cells” (MBC).) The improvement brought by the MBC flash is the storing of two bits in each cell. (In principle MBC also includes the storage of more than two bits per cell. In order to simplify the explanations, the two-bit case is emphasized herein. It should however be understood the present invention is equally applicable to flash memory devices that support more than two bits per cell.) In order for a single cell to store two bits of information the cell must be able to be in one of four different states. As the cell's “state” is represented by its threshold voltage, it is clear an MBC cell should support four different valid ranges for its threshold voltage. FIG. 1B shows the threshold voltage distribution for a typical MBC cell. As expected, FIG. 1B has four peaks, each corresponding to one of the states. As for the SBC case, each state is actually a range of threshold voltages and not a single threshold voltage. When reading the cell's contents, all that must be guaranteed is that the range that the cell's threshold voltage is in is correctly identified. For a prior art example of an MBC flash device see U.S. Pat. No. 5,434,825 to Harari.
When encoding two bits in an MBC cell as one of the four states, it is common to have the left-most state in FIG. 1B (typically having a negative threshold voltage) represent the case of both bits having a value of “1”. (In the discussion below the following notation is used—the two bits of a cell are called the “lower bit” and the “upper bit”. An explicit value of the bits is written in the form [“upper bit” “lower bit”], with the lower bit value on the right. So the case of the lower bit being “0” and the upper bit being “1” is written as “10”. One must understand that the selection of this terminology and notation is arbitrary, and other names and encodings are possible). Using this notation, the left-most state represents the case of “11”. The other three states are illustrated as assigned in the following order from left to right—“10”, “00”, “01”. One can see an example of an implementation of an MBC NAND flash device using such encoding as described above in U.S. Pat. No. 6,522,580 to Chen, which patent is incorporated by reference for all purposes as if fully set forth herein. See in particular FIG. 8 of Chen. It should be noted though that the present invention does not depend on this assignment of the states, and there are other ordering that can be used. When reading an MBC cell's content, the range that the cell's threshold voltage is in must be identified correctly; only in this case this cannot always be achieved by comparing to one reference voltage, and several comparisons may be necessary. For example, in the case illustrated in FIG. 1B, one way to read the lower bit is first to compare the cell's threshold voltage to a reference comparison voltage V1 and then, depending on the outcome of the comparison, to compare the cell's threshold voltage to either a zero reference comparison voltage or a reference to comparison voltage V2. Another way to read the lower bit is to compare the cell's threshold voltage unconditionally to both the zero reference voltage and V2. In either case, two comparisons are needed.
MBC devices provide a great advantage of cost—using a similarly sized cell one stores two bits rather than one. However, there are also some drawbacks to using MBC flash—the average read and write times of MBC memories are longer than of SBC memories, resulting in lower performance. Also, the reliability of MBC is lower than SBC. This can easily be understood—the differences between the threshold voltage ranges in MBC are much smaller than in SBC. Thus, a disturbance in the threshold voltage (e.g. leaking of the stored charge causing a threshold voltage drift, interference from operations on neighboring cells, etc.) that may have gone unnoticed in SBC because of the large gap between the two states, might cause an MBC cell to move from one state to another, resulting in an erroneous bit. The end result is a lower quality specification of MBC cells in terms of data retention time or the endurance of the device to many write/erase cycles. Thus there are advantages to using both MBC cells and SBC cells, and the selection can be different depending on the application's requirements.
While the above explanations deal with floating-gate flash memory cells, there are other types of flash memory technologies. For example, in the NROM flash memory technology there is no conductive floating gate but instead there is an insulating layer trapping the electric charge. The present invention is equally applicable to all flash memory types, even though the explanations herein are given in the context of floating-gate technology.
FIG. 2A, which is identical to FIG. 1 of Chen, is a block diagram of a typical prior art flash memory device. A memory cell array 1 including a plurality of memory cells M arranged in a matrix is controlled by a column control circuit 2, a row control circuit 3, a c-source control circuit 4 and a c-p-well control circuit 5. Column control circuit 2 is connected to bit lines (BL) of memory cell array 1 for reading data stored in the memory cells (M), for determining a state of the memory cells (M) during a program operation, and for controlling voltage levels of the bit lines (BL) to promote the programming or to inhibit the programming. Row control circuit 3 is connected to word lines (WL) to select one of the word lines (WL), to apply read voltages, to apply programming voltages combined with the bit line voltage levels controlled by column control circuit 2, and to apply an erase voltage coupled with a voltage of a p-type region on which the memory cells (M) are formed. C-source control circuit 4 controls a common source line connected to the memory cells (M). C-p-well control circuit 5 controls the c-p-well voltage. Typically, in a NAND flash device, the cells controlled by one word line correspond to one or two pages of the device, and the word lines are organized into blocks, with each block typically including a number of word lines that is a moderate power of 2, e.g., 25=32. A page is the smallest unit of a NAND flash device whose cells can be programmed together. A block is the smallest unit of a NAND flash device whose cells can be erased together.
The data stored in the memory cells (M) are read out by column control circuit 2 and are output to external I/O lines via an I/O line and a buffer in data input/output circuit 6. Program data to be stored in the memory cells are input to the buffer in data input/output circuit 6 via the external I/O lines, and are transferred to the column control circuit 2. The external I/O lines are connected to a controller 20.
Command data for controlling the flash memory device are input to a command interface connected to external control lines that are connected with controller 20. The command data inform the flash memory of what operation is requested. The input command is transferred to a state machine 8 that controls column control circuit 2, row control circuit 3, c-source control circuit 4, c-p-well control circuit 5 and data input/output circuit 6. State machine 8 can output a status data of the flash memory such as READY/BUSY or PASS/FAIL.
Controller 20 is connected or connectable with a host system such as a personal computer, a digital camera, a personal digital assistant. It is the host that initiates commands, such as to store or read data to or from memory array 1, and provides or receives such data, respectively. Controller 20 converts such commands into command signals that can be interpreted and executed by command circuits 7. Controller 20 also typically contains buffer memory for the user data being written to or read from memory array 1. A typical memory system includes one integrated circuit chip 21 that includes controller 20, and one or more integrated circuit chips 22 that each contain a memory array and associated control, input/output and state machine circuits. The trend, of course, is to integrate the memory array and controller circuits of a system together on one or more integrated circuit chips. The memory system may be embedded as part of the host system, or may be included in a memory card that is removably insertable into a mating socket of host systems. Such a card may include the entire memory system, or the controller and memory array, with associated peripheral circuits, may be provided in separate cards.
FIG. 2B, which is identical to FIG. 1 of U.S. Pat. No. 6,751,766 to Guterman et al., is a block diagram of another typical prior art flash memory device. A large number of individually addressable memory cells are arranged in a regular array 11 of rows and columns. Individual memory cells can be controlled by bit lines, select gates arranged in word lines, and steering gates. Bit lines are designated herein to extend along columns of array 11, and word lines are designated to extend along the rows of array 11. Bit line unit 13 may include a bit line decoder, storage elements, driver circuits and sense amplifiers. Bit line unit 13 can be coupled to cell array 11 by line 15, and to controller 27 by bit-control line 29 and by read line 41. Word line unit 19 may include a select gate decoder and driver circuits. Word line unit 19 can be coupled to cell array 11 by line 17, and to controller 27 by word-control line 31. Steering line unit 43 may include a steering gate decoder and driver circuits. Steering unit 43 can be coupled to cell array 11 by line 23, to controller 27 by steering-control line 33, and to bit line unit 13 by line 44. Bit line unit 13, word line unit 19 and steering unit 43 can be coupled to bus 25, which in turn is coupled to controller 27. Controller 27 can be coupled to the host by line 35.
When a preselected memory cell is to be programmed, voltages can be applied to the bit lines, word line and steering gates, corresponding to the preselected memory cell, at predetermined levels sufficient for the programming of the preselected cell. Controller 27 sends the address of the preselected memory cell through bus 25 to the respective decoders in bit line unit 13, word line unit 19, and steering gate unit 43 through lines 26a, 26b, and 26c, respectively. Status and control commands between bit line unit 13, word line unit 19, steering gate unit 43 and controller 27 are communicated through bit-control line 29, word-control line 31 and steering control line 33.
When a preselected memory cell is to be read, voltages can be applied to the corresponding bit lines, word line and steering gates, corresponding to the preselected memory cell, at predetermined levels, sufficient to enable the reading of the preselected memory cell. Controller 27 is capable of applying the voltages of the bit lines through bit-control line 29, applying the voltages of the word lines through word-control line 31 and applying the voltages of steering gates through steering control line 33. A current can be generated through the preselected memory cell by these voltages. The current is indicative of whether the preselected memory cell was programmed or not. The value of the current can be amplified and compared against references by sense amplifiers in bit line unit 13, the result of which can be temporarily stored in latches or registers. The resultant data, read out from the preselected memory cell, can be sent to controller 27 through read line 41.
Shifts in the apparent charge stored on a floating gate can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates. This floating-gate-to-floating-gate coupling phenomenon, which also is referred to herein as “inter-cell cross coupling”, is described by Chen and Fong in U.S. Pat. No. 5,867,429, which patent is incorporated by reference for all purposes as if fully set forth herein. A floating gate adjacent to a target gate may be a neighboring floating gate on the same bit line, a neighboring floating gate on the same word line, or a floating gate that is diagonal from the target floating gate because it is on both a neighboring bit line and on a neighboring word line.
The floating-gate-to-floating-gate coupling phenomenon occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. For example, suppose a first memory cell is programmed to add a level of charge to its floating gate that corresponds to one set of data. Suppose that subsequently, one or more adjacent memory cells are programmed to add a level of charge to their floating gates that correspond to a second set of data. After the one or more of the adjacent memory cells are programmed, the charge level read from the to first memory cell appears to be different than programmed because of the effect of the charge on the adjacent memory cells being coupled to the first memory cell. The coupling from adjacent memory cells can shift the apparent charge level being read a sufficient amount to lead to an erroneous reading of the stored data.
The effect of the floating-gate-to-floating-gate coupling is of greater concern for MBC devices than for SBC devices because in MBC devices the threshold voltage ranges that define the states of the cells are narrower than in SBC devices.
Several approaches are known for compensating for floating-gate-to-floating-gate coupling. Chen and Fong structure a flash memory so that cells whose floating gates otherwise would be coupled are isolated physically from each other. Alternatively, Chen and Fong adjust reference comparison voltages (e.g. V1 and V2 in FIG. 1B) in a manner that compensates for floating-gate-to-floating-gate coupling. Chen, Cernea and Hemnik teach a similar method in U.S. Pat. No. 7,196,946. The Chen, Cernea and Hemnik patent is incorporated by reference for all purposes as if fully set forth herein. Error-correction encoding of data to be stored, followed by error-correction decoding of the data as read, that is used routinely to compensate for inaccuracies generally in reading data from flash memories, also compensates for floating-gate-to-floating-gate coupling.
FIG. 3, which is identical to FIG. 8A of Chen and Fong, shows schematically an array of flash memory cells, including nine such cells labeled with reference numbers 151 through 159. The numbers along the dashed arrows in FIG. 3 are coupling ratios between the cells connected by the arrows. To determine the reference comparison voltages appropriate e.g. for reading cell 151, Chen and Fong read neighbor cells 152 through 159 (or at least cells 152 and 156, the cells most strongly coupled to cell 151) and combine these readings with the respective coupling ratios to cell 151 to determine how much to shift the reference comparison voltages of cell 151 from the default values of these reference comparison voltages.
The above discussion assumes that threshold voltages are read with a resolution on the order of the widths of the threshold voltage ranges that define the states of the cells. It often is advantageous to read the threshold voltages with a finer resolution, as taught e.g. by Ban in US Patent Application No. 2005/0013165. FIG. 4, which is modified from FIG. 2 of Ban, shows the threshold voltage distributions of MBC cells that store three bits each. A cell whose threshold voltage is in threshold voltage distribution 110, between Vmin and V1, is interpreted as being in a state corresponding to the bit pattern “111”. A cell whose threshold voltage is in threshold voltage distribution 112, between V1 and V2, is interpreted as being in a state corresponding to the bit pattern “110”. A cell whose threshold voltage is in threshold voltage distribution 114, between V2 and V3, is interpreted as being in a state corresponding to the bit pattern “101”. A cell whose threshold voltage is in threshold voltage distribution 116, between V3 and V4, is interpreted as being in a state corresponding to the bit pattern “100”. A cell whose threshold voltage is in threshold voltage distribution 118, between V4 and V5, is interpreted as being in a state corresponding to the bit pattern “011”. A cell whose threshold voltage is in threshold voltage distribution 120, between V5 and V6, is interpreted as being in a state corresponding to the bit pattern “010”. A cell whose threshold voltage is in threshold voltage distribution 122, between V6 and V7, is interpreted as being in a state corresponding to the bit pattern “001”. A cell whose threshold voltage is in threshold voltage distribution 124, between V7 and Vmax, is interpreted as being in a state corresponding to the bit pattern “000”. Ban teaches reading such MBC cells by comparing the cells' threshold voltages not just to reference comparison voltages V1, V2, V3, V4, V5, V6 and V7, that bound the threshold voltage ranges that define the states of the cells, and that Ban calls “integral” reference comparison voltages, but also to what Ban calls “fractional” reference comparison voltages (V0.5, V1.5, V2.5, V3.5, V4.5, V6.5 and V7.5). The results of reading flash cells with a resolution on the order of the widths of the threshold voltage ranges that define the states of the cells often is called “hard bits” and the results of reading flash cells with a finer resolution often is called “soft bits”.